An Implementation of Pipelined Rijndael with SystemC and Co-emulation with iPROVE

This paper describes an implementation of Rijndael, a new Advanced Encryption Standard (AES), with SystemC. The design started in the un-timed functional level description in C and was gradually refined until all blocks were translated into RTL SystemC, which can be synthesized with CoCentric SystemC Compiler. To improve the verification speed, cycle-accurate co-emulation was used. iPROVE, an FPGAbased emulator by Dynalith Systems, maps the DUT into FPGA to relieve the simulator from handling simulation events generated by the DUT, and thus accelerates the verification speed. The verification speed of the pipelined Rijndael implementation, which takes 8,009 slices of Xilinx VirtexE FPGA, was accelerated 70 times with the co-emulation.